In general, an important factor in designing a charge pump circuit is minimizing the mismatch of up/down currents. FIG. 1 illustrates several aspects of mismatch and feed-through of up/down currents in a conventional charge pump. Due to internal delays that may be unavoidable, regardless of the type of phase frequency detector (PFD) in use, an interval may exist where both “up” and “down” current signals merge, as shown in FIG. 1(a). At the interval of internal delay, the paths of the up/down currents of a charge pump merge into each other, as shown in FIG. 1(b).
If the size of the up/down currents are exactly the same, no charge will flow to a loop filter and the control voltage will not be affected. However, a difference between the two currents will occur and cause periodic noise within the control voltage as shown in FIG. 1(c), even if the phase of the voltage waveform is locked. The periodic noise appears in the output signal of the PLL in the form of spurious noise, and its position is the same as the frequency of the input signal of the phase frequency detector (PFD). For example, in a frequency synthesizer PLL of the integer-N mode, when the comparison frequency is 1 MHz, the spurious noise appears with a 1 MHz offset from the carrier frequency.
Another conventional aspect of typical charge pump circuits is the feed-through noise of the up/down currents. This aspect refers to a phenomenon whereby the up/down signals swing between a power source (VDD) and a ground (GND). The up/down signal is delivered by a parasitic capacitor to an output, which adversely affects the control voltage. Every switch of up/down signals can cause periodic noise to be introduced into the control voltage, which subsequently generates spurious noise, requiring minimization of feed-through.
Additionally, mismatched up/down currents can be created using conventional charge pump techniques. For example, a mismatch may occur as a result of limited transistor output resistance, charge-sharing during switching, and mismatched transistors. A mismatch caused by limited transistor output resistance can occur if a source/sink of a charge pump includes an ideal current source, where the current may be constant without regard to voltage output (e.g., without regard to voltages at both terminals of the current source). However, an ideal current source may not be a realistic situation and current output can change slightly along with changes of the voltage output. FIG. 2 illustrates a graph of current output with regard to voltage output of a conventional charge pump, plotting a real versus an ideal case scenario, as described above. Thus, except for one point in the voltage output, inevitably, a difference exists between the up/down currents.
One conventional technique for solving mismatched up/down currents is illustrated in FIG. 3. As shown in FIG. 3, an output terminal of a charge pump can be implemented in cascade mode in order to increase output resistance. However, this implementation may be problematic in terms of reducing the dynamic range of the output of the charge pump.
Another problematic area of conventional charge pumps can be charge-sharing effects. A charge sharing effect may be created by an instantaneous change in the voltage output due to a difference in charged voltages between an output load capacitor and a parasitic capacitor of a switching transistor when switching up/down signals. Referring to FIG. 4, when transistor M1 is off and transistor M2 is on, a down current flows changing the charged voltage, Vout, of a capacitor (CL). Simultaneously, VA is charged to Vdd, as M1 is on and M2 is off. If M1 and M2 are both on and CP and CL are charged with different voltages (VA and Vcont, respectively), then an instantaneous charge distribution occurs. The charge distribution causes an unwanted change in the voltage output by as much as ΔV. In order to avoid this, VA should be charged to Vout instead of Vdd using a feedback even when M2 is off, as illustrated in FIG. 5.
As illustrated in FIG. 5, VA can be charged to Vout instead of Vdd, using a feedback including when M2 is off. However, while charging to Vout can reduce the charge distribution effect, feed-through of the switching signals is unavoidable because the switching transistor is directly connected to the output node.
The transistor mismatch discussed above refers to transistor mismatch. A current mismatch occurs due to size mismatch following process changes when the current mirror generates up/down currents. To reduce transistor mismatch, a conventional technique provides for reducing mismatch by trimming the up or down current after a processor has been manufactured. However, this technique is problematic in that every processor would require measurement and trimming.
Another conventional embodiment includes a charge pump circuit, as illustrated in FIG. 6, which was designed with an emphasis on the mismatch of up/down currents. The conventional circuit embodied in FIG. 6 uses replica bias to equalize up/down currents, regardless of changes in output node voltage. In other words, as Vout and Vr become equal via the feedback network and as the PMOS current and the PMOS gate voltage are determined by the replica bias, the up/down currents equalize using the voltage outputs from corresponding areas of the charge pump with the same structure. However, the conventional circuit shown in FIG. 6 is insufficient to prevent feed-through of up/down currents in light of the charge-sharing problem described above. Further, giving the buffer a sufficiently wide dynamic range is difficult, when attempting to equalize the DC level of Qn and Qp. Conventional charge pumps are problematic in that the range of voltage output may be small and inhibit the feedback loop from operating properly. Thus, the feed-through of the up/down signals may affect Qn causing the feedback loop to operate incorrectly.